(1) Field of the Invention
This invention relates to a semiconductor memory device, particularly to a memory device having a discharge means for improving the falling characteristic of the potential of a word line.
(2) Description of the Prior Art
A memory device, providing a so-called emitter detection type memory cell wherein a pair of npn type bipolar transistors are cross-coupled and the emitters of such pair of transistors are connected to a pair of bit lines, is often used. A memory device of this type facilitates the coupling between peripheral circuits constituted by ECL (Emitter Coupled Logic) circuits and memory cells, and simultaneously realizes a high speed readout operation. These are outstanding advantages of this type of memory device. Moreover, diversified improvements have been attempted in order to realize further high speed readout operation. For example, the reference readout level given to a transistor which connects a sense amplifier and a bit line is temporarily lowered when a potential of a word line changes. This method is mainly intended to curtail the rise time of potential of the word line, but as a method for curtailing the fall time of potential of the word line, the fall time of potential of the word line is shortened by giving a discharge current to the selected word lines of memory which are to be operated under larger capacity and lower current.
In regard to a first word line (W.sup.+) and a second word line (W.sup.-) to which a memory cell is connected, the first word line (W.sup.+) is provided with detecting means which detects a potential of first word line (W.sup.+) and the delay means which delays a detected output, while the second word line (W.sup.-) is provided with discharge means which allows a discharge current to flow from the first word line (W.sup.+) via the memory cell, and the second word line (W.sup.-) in accordance with an output of the delay means. In such a structure, when the selected word line is to be shifted to the non-selected condition, the discharge means turns ON in accordance with the detected output of the detecting means, allowing the discharge current to flow. As the word line turns into the non-selected condition, the potential of the first word line (W.sup.+) is lowered and when it becomes lower than the specified voltage, no detected output can be obtained.
However, the delay means causes a detected output to be applied to the discharge means even when the first word line (W.sup.+) is set to a potential which is lower than the specified value, and resultingly a discharge current flows continuously for some specified period.
Thereby, the first word line voltage is rapidly lowered and the fall time of the word line potential is curtailed. In such an existing memory device, on the occasion that the word line is to be shifted to the selected condition from non-selected condition, when a voltage of the first word line (W.sup.+) gradually rises and exceeds the specified voltage, the detecting means makes the discharge means turn on and the discharge current starts to flow during the rise of the word line voltage.
Since this discharge current flows into the transistor which is turned ON among the cross-coupled transistors within the memory cell from the first word line (W.sup.+), a large amount of charges are stored in the base and collector of the transistor which is turned ON.
Therefore, when inverted data is written into this memory cell, in other words, when the transistors which are turned ON among the crosscoupled transistors are turned OFF, a large amount of charges being stored must be absorbed. For this purpose, it is required to give a heavy write current to the memory cell.
Moreover, a heavy discharge current on the first word line (W.sup.+) brings about reduction of the word line potential due to a voltage drop of the word line.
Further, a heavy discharge current flowing through the first word line (W.sup.+) causes a heavy base current to flow into the word line driver transistor, resulting in reduction of base potential due to a voltage drop by the resistor existing between the base of the word line driver transistor and ground.
Thereby, a potential of the word line which is lower than the base potential by V.sub.BE of the word line driver transister is lowered even.
When the discharge current flows as explained above, the voltage of the first word line (W.sup.+) is lowered and resultingly the voltage of the selected word lines comes close to the voltage under the non-selected condition, thus reducing noise margin.